数字时钟下载 全屏数字时钟 V1.0 绿色便携免费版 下载

来源:脚本之家  责任编辑:小易  

www.zgxue.com防采集请勿采集本网。

软件大小:24.7MB 软件语言:简体中文 软件类型:国产软件 软件授权:免费软件 更新时间:2020-09-26 13:00:53 软件类别:桌面工具 软件官网:未知官方 网友评分:软件评分 应用平台:Windows平台

全屏数字时钟是由网友开发分享的一款桌面时钟软件,支持透明度设置、多秒表、计次、多倒计时、多闹钟功能,科幻的背景配合起来很有氛围!本站提供的是这款软件的绿色版,需要的朋友快来下载吧!

软件介绍

  用Python写的全屏数字时钟软件,含透明度设置、多秒表、计次、多倒计时、多闹钟功能,在托盘图标上中击隐藏主界面。

  闹钟设定后没有及时关闭会响铃1分钟,1分钟过后还没关闭会每隔5分钟响铃1分钟,直到关闭闹钟。

  背景图片wallpaper.jpg可自行替换,注意文件名必须为wallpaper,支持jpg和png格式。

下载地址如下:

网硕互联电信下载

港中数据电信下载

河南紫田网通下载

易阳网络电信下载

酷云中国电信下载

易阳IDC电信下载

群英网络电信下载

烽火云集电信下载

网盾科技电信下载

创梦网络电信下载

***********百分秒*************************entity count100 is Port ( shift_temp,clk: in STD_LOGIC; q:out std_logic_vector(7 downto 0);4102 co:out std_logic);end count100;architecture Behavioral of count100 is signal temp:std_logic_vector(7 downto 0):=(others=>'0');begin process(clk) begin if clk'event and clk='1' then if temp(3 downto 0)=9 then if temp(7 downto 4)=9 then temp<=(others=>'0');co<='1';else temp(7 downto 4)<=temp(7 downto 4)+1;temp(3 downto 0)<=(others=>'0');co<='0';end if;else temp(3 downto 0)<=temp(3 downto 0)+1;co<='0';end if;end if; end process; q<=temp;end Behavioral;****************************秒,分1653*******************entity count60 is Port ( shift_temp,key_m,clk: in STD_LOGIC; q:out std_logic_vector(7 downto 0); co:out std_logic);end entity;architecture Behavioral of count60 is signal temp:std_logic_vector(7 downto 0):=(others=>'0'); signal temp_clk,temp_co:std_logic;begin process(shift_temp) begin if shift_temp='1' then temp_clk<=key_m;co<='0';else temp_clk<=clk;co<=temp_co;end if; end process; process(temp_clk) begin if temp_clk'event and temp_clk='1' then if temp(3 downto 0)=9 then if temp(7 downto 4)=5 then temp<=(others=>'0');temp_co<='1';else temp(7 downto 4)<=temp(7 downto 4)+1;temp(3 downto 0)<=(others=>'0');temp_co<='0';end if;else temp(3 downto 0)<=temp(3 downto 0)+1;temp_co<='0';end if;end if; end process; q<=temp;end Behavioral;******************************小时**********************************entity count24 is Port ( shift_temp,key_m,clk: in STD_LOGIC; q:out std_logic_vector(7 downto 0));end count24;architecture Behavioral of count24 issignal temp_q:std_logic_vector(7 downto 0):=(others=>'0');signal temp:std_logic_vector(4 downto 0);signal temp_clk:std_logic;begin process(shift_temp) begin if shift_temp='1' then temp_clk<=key_m;else temp_clk<=clk;end if; end process; process(temp_clk) begin if temp_clk'event and temp_clk='1' then if temp="10111" then temp<="00000";temp_q<=(others=>'0');elsif temp="01001" or temp="10011" then temp_q(3 downto 0)<="0000";temp_q(7 downto 4)<=temp_q(7 downto 4)+1;temp<=temp+1;else temp_q(3 downto 0)<=temp_q(3 downto 0)+1;temp<=temp+1;end if;end if;end process;q<=temp_q;end Behavioral;************************分频****************************entity clock is Port ( clk : in STD_LOGIC; clk_out:out std_logic_vector(3 downto 0));end clock;architecture Behavioral of clock is signal temp_clk:std_logic_vector(3 downto 0); signal temp0,temp1,temp2,temp3:std_logic_vector(24 downto 0):=(others=>'0');beginprocess(clk) begin if clk'event and clk='0' then if temp0=24999999 then temp_clk(0)<=not temp_clk(0);temp0<=(others=>'0'); else temp0<=temp0+1; end if; end if;end process;process(clk) begin if clk'event and clk='0' then if temp1=249999 then temp_clk(1)<=not temp_clk(1);temp1<=(others=>'0');else temp1<=temp1+1;end if;end if;end process;process(clk)beginif clk'event and clk='0' then if temp2=124999 then temp_clk(2)<=not temp_clk(2);temp2<=(others=>'0'); else temp2<=temp2+1; end if; end if;end process;process(clk)beginif clk'event and clk='0' then if temp3=249 then temp_clk(3)<=not temp_clk(3);temp3<=(others=>'0'); else temp3<=temp3+1; end if; end if;end process;clk_out<=temp_clk;end Behavioral;***********************调时闪烁**********************entity clos is Port (clk:in std_logic; q : in STD_LOGIC_vector(2 downto 0); q_out:out std_logic_vector(5 downto 0));end clos;architecture Behavioral of clos is signal temp:std_logic_vector(5 downto 0);begin process(q) begin case q iswhen "000"=>temp<=(others=>'0');when "001"=>temp(0)<=clk;temp(1)<=clk;temp(5 downto 2)<="0000";when "010"=>temp(3)<=clk;temp(2)<=clk;temp(5 downto 4)<="00";temp(1 downto 0)<="00"; when "100"=>temp(5)<=clk;temp(4)<=clk;temp(3 downto 0)<="0000";when others=>null;end case; end process; q_out<=temp;end Behavioral;*************************去抖动***********************************entity kicker is Port ( clk,din : in STD_LOGIC; d_out:out std_logic);end kicker;architecture Behavioral of kicker issignal x,y,d:std_logic:='0';begin process(clk) begin if clk'event and clk='1' then x<=din;y<=x;d<=x and y; end if; end process;d_out<=d; end Behavioral;******************调时控制信号************************entity shift is Port ( key_in : in STD_LOGIC; shift_out: out std_logic_vector(3 downto 0));end shift;architecture Behavioral of shift issignal data:std_logic_vector(3 downto 0):="0001";beginprocess(key_in)begin if key_in'event and key_in='1' then data(2 downto 0)<=data(3 downto 1); data(3)<=data(0); end if;end process;shift_out(3 downto 0)<=data(3 downto 0);end Behavioral;*****************32位数据输出文件******************entity count32 is Port ( m,s,clk: in STD_LOGIC; data:out std_logic_vector(31 downto 0); close:out std_logic_vector(2 downto 0));end count32;architecture Behavioral of count32 is component count100 Port ( shift_temp,clk: in STD_LOGIC; q:out std_logic_vector(7 downto 0); co:out std_logic); end component; component count60 Port ( shift_temp,key_m,clk: in STD_LOGIC; q:out std_logic_vector(7 downto 0); co:out std_logic); end component; component count24 Port ( shift_temp,key_m,clk: in STD_LOGIC; q:out std_logic_vector(7 downto 0)); end component; component kicker Port ( clk,din : in STD_LOGIC; d_out:out std_logic); end component; component shift Port ( key_in : in STD_LOGIC; shift_out: out std_logic_vector(3 downto 0)); end component; component clock Port ( clk : in STD_LOGIC; clk_out:out std_logic_vector(3 downto 0)); end component; signal temp:std_logic_vector(31 downto 0); signal pinl:std_logic_vector(3 downto 0); signal anjian:std_logic_vector(3 downto 0); signal temp_co:std_logic_vector(2 downto 0); signal qa,qc:std_logic;begin u1:count100 port map(anjian(0),pinl(1),temp(7 downto 0),temp_co(0)); u2:count60 port map(anjian(1),qa,temp_co(0),temp(15 downto 8),temp_co(1)); u3:count60 port map(anjian(2),qa,temp_co(1),temp(23 downto 16),temp_co(2)); u4:count24 port map(anjian(3),qa,temp_co(2),temp(31 downto 24)); u5:clock port map(clk,pinl); u6:kicker port map(pinl(2),m,qa); u7:kicker port map(pinl(2),s,qc); u8:shift port map(qc,anjian); data<=temp;close<=anjian(3 downto 1);end Behavioral;*********************8位数码管扫描**********************entity weix is Port ( clk : in STD_LOGIC; close:in std_logic_vector(5 downto 0); data : in STD_LOGIC_vector(31 downto 0); bt : out STD_LOGIC_vector(7 downto 0); sg: out STD_LOGIC_vector(7 downto 0));end weix;architecture Behavioral of weix is signal cnt8:std_logic_vector(2 downto 0):="000"; signal temp:std_logic_vector(3 downto 0); signal led7s:std_logic_vector(6 downto 0); signal a:std_logic; signal wei:std_logic_vector(7 downto 0):="11111110";begin process(cnt8) begin case cnt8 is when"000"=>wei<="11111110";temp<=data(3 downto 0);a<='0'; when"001"=>wei<="11111101";temp<=data(7 downto 4);a<='0';when"010"=> if close(0)='0' then wei<="11111011"; else wei<="11111111";end if;temp<=data(11 downto 8);a<='1'; when"011"=> if close(1)='0' then wei<="11110111"; else wei<="11111111";end if;temp<=data(15 downto 12);a<='0'; when"100"=> if close(2)='0' then wei<="11101111"; else wei<="11111111";end if;temp<=data(19 downto 16);a<='1'; when"101"=> if close(3)='0' then wei<="11011111"; else wei<="11111111";end if;temp<=data(23 downto 20);a<='0'; when"110"=> if close(4)='0' then wei<="10111111"; else wei<="11111111";end if;temp<=data(27 downto 24);a<='1'; when"111"=> if close(5)='0' then wei<="01111111"; else wei<="11111111";end if;temp<=data(31 downto 28);a<='0'; when others=>wei<= "11111111"; end case; end process; process(clk) begin if clk'event and clk='1' then cnt8<=cnt8+1; end if; end process; process(temp) begin case temp is when "0000" => led7s<="0111111"; when "0001" => led7s<="0000110"; when "0010" => led7s<="1011011"; when "0011" => led7s<="1001111"; when "0100" => led7s<="1100110"; when "0101" => led7s<="1101101"; when "0110" => led7s<="1111101"; when "0111" => led7s<="0000111"; when "1000" => led7s<="1111111"; when "1001" => led7s<="1101111"; when others=>null; end case; end process;sg(6 downto 0)<=led7s;sg(7)<=a;bt<=wei;end Behavioral;*******************电子时钟顶层文件****************entity shizhong is Port (oe:out std_logic_vector(2 downto 0); er:out std_logic_vector(2 downto 0); m,s,clk : in STD_LOGIC; bt:out std_logic_vector(7 downto 0); sg:out std_logic_vector(7 downto 0));end shizhong;architecture Behavioral of shizhong is component count32 Port ( m,s,clk: in STD_LOGIC; data:out std_logic_vector(31 downto 0); close:out std_logic_vector(2 downto 0)); end component; component clos Port (clk:in std_logic; q : in STD_LOGIC_vector(2 downto 0); q_out:out std_logic_vector(5 downto 0)); end component; component clock Port ( clk : in STD_LOGIC; clk_out:out std_logic_vector(3 downto 0)); end component; component weix Port ( clk : in STD_LOGIC; close:in std_logic_vector(5 downto 0); data : in STD_LOGIC_vector(31 downto 0); bt : out STD_LOGIC_vector(7 downto 0); sg: out STD_LOGIC_vector(7 downto 0)); end component; signal temp:std_logic_vector(31 downto 0); signal qa:std_logic_vector(2 downto 0); signal qb:std_logic_vector(5 downto 0); signal temp_clk:std_logic_vector(3 downto 0);begin u1:count32 port map(m,s,clk,temp,qa); u2:weix port map(temp_clk(3),qb,temp,bt,sg); u3:clock port map(clk,temp_clk); u4:clos port map(temp_clk(0),qa,qb); oe<="000";er<="110";end Behavioral;************索引脚******************供参考NET "bt<0>" LOC = "L21" ;NET "bt<1>" LOC = "K22" ;NET "bt<2>" LOC = "K21" ;NET "bt<3>" LOC = "J22" ;NET "bt<4>" LOC = "J21" ;NET "bt<5>" LOC = "H22" ;NET "bt<6>" LOC = "H21" ;NET "bt<7>" LOC = "G22" ;NET "clk" LOC = "A11" ;NET "er<0>" LOC = "V20" ;NET "er<1>" LOC = "F17" ;NET "er<2>" LOC = "L18" ;NET "m" LOC = "U21" ;NET "oe<0>" LOC = "Y21" ;NET "oe<1>" LOC = "L22" ;NET "oe<2>" LOC = "M20" ;NET "s" LOC = "T22" ;NET "sg<0>" LOC = "R21" ;NET "sg<1>" LOC = "R22" ;NET "sg<2>" LOC = "P21" ;NET "sg<3>" LOC = "P22" ;NET "sg<4>" LOC = "N21" ;NET "sg<5>" LOC = "N22" ;NET "sg<6>" LOC = "M21" ;NET "sg<7>" LOC = "M22" ;内容来自www.zgxue.com请勿采集。


  • 本文相关:
  • 用VHDL写数字电子时钟
  • 网站首页软件下载安卓下载mac软件驱动下载字体下载源码下载游戏下载dll下载软件专题网站地图网络软件系统工具应用软件联络聊天图形图像多媒体类游戏娱乐安全相关教育教学手机软件u盘量产编程软件安卓游戏安卓软件手机网游休闲益智影音播放社交聊天安全防护系统工具输入法生活服务学习理财mac网络工具mac图形图像mac多媒体类mac应用软件显卡驱动声卡驱动网卡驱动主板驱动摄像头驱动扫描仪驱动手机驱动数码驱动笔记本驱动打印机一体机驱动中文字体英文字体图案字体qq字体其它字体asp源码.net源码php源码jsp源码网页编辑器数据库管理源码黑客源码其它源码安卓游戏苹果游戏手机游戏单机游戏模拟器街机roms游戏平台游戏工具格斗类游戏补丁游戏攻略abcdefghijklmnopqrstuvwxyz0-9其它ps软件dll下载网站开发常用软件软件教程主页软件下载系统工具桌面工具酷黑桌面时钟 v1.0 免费绿色版clockwise(多种时钟提醒工具) v3.25c 免费安装版healthy message(桌面时钟) v1.0 绿色免费版fliptime(翻牌时钟屏保) v1.2 官方安装版数字时钟时钟fences win 桌面图标自动整理软件 v3.09.11 汉化绿色特别版fences win 桌面图标自动整理软件 v3.09.11 汉化绿色特别版下载windows 7 dreamscene activator(梦幻桌面激活器) v1.1 中文免费windows 7 dreamscene activator(梦幻桌面激活器) v1.1 中文免费下载mirrorop receiver windows 1.2 pc版 mirrorop receiver windows 1.2 pc版 下载wallpaper calendar 桌面日历下载 v3.0.2 汉化绿色特别版wallpaper calendar 桌面日历下载 v3.0.2 汉化绿色特别版下载xp系统屏保软件 微软官方版xp系统屏保软件 微软官方版下载飞雪桌面日历注册机 飞雪桌面日历注册码生成器 v2.62 中文绿色免飞雪桌面日历注册机 飞雪桌面日历注册码生成器 v2.62 中文绿色免下载win10桌面美化插件合集win10桌面美化插件合集下载随意画(电子画线工具) v1.0绿色版下载随意画(电子画线工具) v1.0绿色版下载下载windowhider(窗口隐藏工具) 3.41 免费绿色版windowhider(窗口隐藏工具) 3.41 免费绿色版下载找不到分享码?全屏数字时钟 v1.0 绿色便携免费版theme studio(华为主题开发软件) v11.0.0.100 免费安装版ashampoo taskbar customizer v1.0 中文破解版(附安装教程+补丁)腾讯桌面整理工具 v3.1.1427.127 免费独立版deskpins(窗口置顶工具) 1.32 绿色汉化版啊噗啊噗upupoo 动态桌面 v2.0 永久激活破解版(含使用教程)desktopcl(桌面自动整理工具) v1.0 免费绿色版stardock fences3(桌面图标管理器) v3.0.3 汉化绿色破解版object desktop(桌面增强) v4.01 免费安装版(附安装教程)bongo cat mver直播工具 v0.1.6.0 绿色免费版(附使用教程)分享码的获取方法迅雷winrar v5全屏数字时钟 v1.0 绿色便携免费版theme studio(华为主题开发软件) v11.0.0.100 免费安装版ashampoo taskbar customizer v1.0 中文破解版(附安装教程+补丁)theaeroclock(透明桌面时钟) v6.03 多语言中文绿色版(32位+64位)everdo(待办事项管理软件) v1.4.1 特别安装版(附激活教程)腾讯桌面整理工具 v3.1.1427.127 免费独立版敬业签(桌面便签) v2.6.1 免费安装版upupoo 动态视频桌面 最新版 v1.3.5.0 安装免费版desktopcal(桌面日历) v2.3.78.5176 中文官方安装免费版deskpins(窗口置顶工具) 1.32 绿色汉化版360浏览器
    免责声明 - 关于我们 - 联系我们 - 广告联系 - 友情链接 - 帮助中心 - 频道导航
    Copyright © 2017 www.zgxue.com All Rights Reserved